 
****************************************
Report : area
Design : or1200_dmmu_top_1
Version: F-2011.09-SP2
Date   : Tue Apr 15 00:57:32 2014
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Information: Updating design information... (UID-85)
Information: Input delay ('fall') on clock port 'clk' will be added to the clock's propagated skew. (TIM-112)
Information: Input delay ('rise') on clock port 'clk' will be added to the clock's propagated skew. (TIM-112)
Library(s) Used:

    saed32rvt_tt1p05v25c (File: /net/humpback.ece.virginia.edu/scratch2/ab9ca/simulation/Synopsys/SynthMMUs/DMMU/dc/ref/models/saed32rvt_tt1p05v25c.db)

Number of ports:                          181
Number of nets:                           232
Number of cells:                           72
Number of combinational cells:             70
Number of sequential cells:                 1
Number of macros:                           0
Number of buf/inv:                         11
Number of references:                      12

Combinational area:        324.541893
Noncombinational area:       7.116032
Net Interconnect area:      84.309963  

Total cell area:           331.657925
Total area:                415.967888
1
